For previous generations of high-performance industrial computing platforms, increasing performance requirements could generally be satisfied through occasional improvements to I/O interconnect standards, and incremental upgrades to new generations of faster processors and larger memory. However, the parallel bus interconnects covered by the PICMG 1.0 and PICMG 1.2 standards have reached their performance ceilings and are now a major bottleneck to overall system performance. Consequently, these standards are no longer able to meet the bandwidth requirements for all of today's high throughput I/O devices and core-logic chipsets, much less supply sufficient headroom necessary to support future generations of I/O devices.

The higher frequencies and lower voltages needed to achieve greater performance levels are not possible using older PCI interconnect technologies like PCI 2.2 and PCI-X, which has created a shift to serial interconnect architecture, more specifically PCI Express. Now, for the first time, SHB Express brings all the features and advantages of PCI Express, including high bandwidth and scalability, to industrial computing platforms.

Looking back, PCI evolved from 32-bit PCI connections running at 33MHz (offering a maximum throughput of 133MB/s) and then stepped up to 64-bit PCI-X connections running at 133MHz (offering a maximum throughput of 1066MB/s). Beyond that, the PCI-X 2.0 standard offers a maximum theoretical output of 4.3GB/s. Ultimately, by leveraging point-to-point serial PCI Express technology, SHB Express can scale up to 10,266MB/s (or 10 GB/s) via 20 PCI Express lanes and PCI bus; in the future, bandwidths well beyond these new limits will become possible.

Aside from significant boosts in I/O bandwidth, it would be ideal to have a standard that allowed full-backwards compatibility with previous interconnect standards, like PICMG 1.0 and 1.2 (i.e. PCI and PCI-X devices), especially since many of these devices are still able to perform their tasks perfectly well. SHB Express solves the compatibility problem by providing full backwards integration with PICMG 1.0 and 1.2 standards, allowing legacy 32-bit PCI and 64-bit PCI-X cards to co-exist in the same system with the newer generation of PCI Express based cards. As the shift from PICMG 1.0 and 1.2 to SHB Express does not require chassis or significant mechanical design changes, and many previous generation components can continue to be used, it makes the upgrade process significantly easier for system designers and ensures that investments of money and time for PCI and PCI-X devices are not wasted outright.

As with PICMG 1.0 and 1.2 standards, SHB Express places emphasis on flexible options for system developers through a modular design approach with multiple backplane and expansion slot options. SHB Express highlights even stronger expandability and flexibility because it permits a great variety of different combinations between CPU cards and backplanes. SHB Express also offers fast MTTR and easier maintenance, because the CPU is located on the SHB. In troubleshooting situations, customers can easily check and locate problems, plus quickly change components such as backplanes, expansion cards or system boards. This modular design also minimizes system development times by placing the I/O connectors on the backplane, further reducing the debugging process. What’s more, because most components are off-the-shelf, commercially available PC parts, the cost-per-performance advantages are realized.

In brief, SHB Express technology carries on the legacy of PICMG 1.0 and 1.2 standards while enabling very high-bandwidth connections between the SHB and backplane, as well as a complete range of PCI Express, PCI-X and PCI devices. It provides high-performance, scalable and cost-effective platforms for the next generation of servers, workstations and industrial computing systems.